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Silicon Labs /EFR32BG21A020F1024IM32 /CMU_S /SYSCLKCTRL

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Interpret as SYSCLKCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKSEL 0 (DIV1)PCLKPRESC 0 (DIV1)HCLKPRESC

HCLKPRESC=DIV1, PCLKPRESC=DIV1

Description

No Description

Fields

CLKSEL

Clock Select

1 (FSRCO): FSRCO is clocking SYSCLK

2 (HFRCODPLL): HFRCODPLL is clocking SYSCLK

3 (HFXO): HFXO is clocking SYSCLK

4 (CLKIN0): CLKIN0 is clocking SYSCLK
PCLKPRESC

PCLK Prescaler

0 (DIV1): PCLK is HCLK divided by 1

1 (DIV2): PCLK is HCLK divided by 2
HCLKPRESC

HCLK Prescaler

0 (DIV1): HCLK is SYSCLK divided by 1

1 (DIV2): HCLK is SYSCLK divided by 2

3 (DIV4): HCLK is SYSCLK divided by 4

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data